Delta-sigma modulation or .DELTA..SIGMA.-modulation, known also as sigma-delta or .SIGMA..DELTA.-modulation, means the known principle of reconverting a previous integration and quantization result into analog domain and subtracting it from the next sample to be quantized before feeding said next sample into the actual integration and quantization unit. Analog to digital converters or ADCs based on the .DELTA..SIGMA.-principle are known to be well suited for applications where the maximum baseband frequency is relatively low (e.g. 20 kHz in digital audio applications) but the required resolution is high (e.g. 16-18 bits). They are also suitable for other kind of applications.
Conventional .DELTA..SIGMA.-modulators relied on heavy oversampling and one-bit quantization to ensure linearity and simple circuit implementation, as is described for example in J. C. Candy, G. C. Temes: "Oversampling Methods for A/D and D/A Conversion", Oversampling Delta-Sigma Data Converters, IEEE Press, New York 1992. However, heavy oversampling is synonymous with high clock frequency, which may set a limit to the usability of one-bit quantization solutions when the signal frequency to be sampled should increase. At the priority date of this patent application there is a growing interest towards multi-bit quantization in .DELTA..SIGMA.-modulators, described e.g. in M. Sarhang-Nejad, G. C. Temes: "A High-Resolution Multibit .SIGMA..DELTA. ADC with Digital Correction and Relaxed Amplifier Requirements", IEEE Journal of Solid-State Circuits, Vol. 28, No. 6, June 1993; or F. Chen, B. H. Leung: "A High Resolution Multibit Sigma-Delta Modulator with Individual Level Averaging", IEEE Journal of Solid-State Circuits, Vol. 30, No.4, April 1995; or R. T. Baird, T. S. Fiez: "A Low Oversampling Ratio 14b 500-kHz .DELTA..SIGMA. ADC with a Self-Calibrated Multibit DAC", IEEE Journal of Solid-State Circuits, Vol. 31. No. 3, March 1996; or O. Nys, R. K. Henderson: "A 19-Bit Low-Power Multibit Sigma-Delta ADC Based on Data Weighted Averaging, IEEE Journal of Solid-State Circuits, Vol. 32. No. 7, July 1997.
FIG. 1 illustrates the basic principle of multibit .DELTA..SIGMA.-modulation. An analog signal is fed into the modulator 100 through line 101 which leads into the the positive input terminal of an adder unit 102. The output of the adder unit is coupled to a loop filter 103 which implements an integration; the transfer function of the loop filter is usually designated as H(z) because transfer functions are most easily handled through their z-transforms. The output of the loop filter is still an analog signal and it is coupled to an analog to digital converter 104 which converts it into a digital word of B bits. This digital word constitutes the output of the modulator 100 at the output line 105. The digital word is also coupled to the input of a digital to analog reconverter 106 which reconverts it into an analog signal to be coupled to the negative input terminal of the adder unit 102.
The nonlinearity effects of multibit .DELTA..SIGMA.-modulators are largely caused by the nonlinearity of the internal DAC or digital to analog converter which reconverts a previously quantized sample into the analog domain before it gets subtracted from the following sample to be quantized. Several approaches have been proposed to compensate for said nonlinearity effects. FIG. 2 illustrates the known basic principle of digitally correcting the output of a sigma-delta modulator 200 by introducing a correction unit 201 between the output of the ADC 104 and the output line 105. The correction unit 201 may use for example a RAM (random access memory) to convert the nonlinearly distorted output readings of the ADC 104 into correct output words. Another approach to solving the nonlinearity problem is known as dynamic element matching or DEM, meaning that the elements that are used for the digital to analog conversion are alternated.
It is also known to chain multiple adder-integrator pairs to obtain a .DELTA..SIGMA.-modulator of a higher order. Such higher order .DELTA..SIGMA.-modulators give a better signal to noise ratio for a given oversampling rate. FIG. 3 illustrates a known second-order .DELTA..SIGMA.-modulator 300 where from the input line 301 there is a series connection of a first adder unit 302, a first loop filter 303, a second adder unit 304, a second loop filter 305 and a multibit ADC converter 306 to the output line 307. The input line 301 is coupled to the positive terminal of the first adder 302, and the output of the first loop filter 303 is coupled to the positive terminal of the second adder 304. From the output of the multibit ADC converter 306 there is also a coupling to a multibit DAC 308, the output of which is coupled to the negative terminals of both adder units 302 and 304.
A feature common to all known multibit .DELTA..SIGMA.-modulators is that the analog to digital conversion has to be performed during a single clock cycle. The conversion result must be available to the feedback DAC well before the next integration phase in order to keep the feedback loop from going unstable. FIG. 4 illustrates a known Flash-type ADC which is the only architecture known at the priority date of this patent application for implementing the analog to digital conversion in a single clock cycle. The input line 410 is coupled to the positive input of N parallel differential amplifiers 401, 402, . . . 40N coupled as comparators. A different reference voltage level Vref1, Vref2 . . . VrefN is coupled to the negative input of each comparator so that the output level of a comparator is either low or high depending on whether the instantaneous voltage level in the input line 410 is lower or higher than the reference voltage level coupled to that particular comparator. The outputs of the comparators constitute a so-called thermometer signal in which ideally all comparator outputs below a certain level (i.e. comparators 401 to 40P, where P.ltoreq.N) are high and the rest of the comparator outputs are low. The comparator outputs are coupled to a decoder 411 which converts the thermometer signal into a digital word of B bits written into an output line 412. Various solutions are known to compensate for the so-called bubble errors or discontinuities in the row of comparator outputs that have the same value.
It is easily seen that in order to implement analog to digital conversion with the resolution of B bits, 2.sup.B -1 comparators are needed, i.e. N=2.sup.B -1 in FIG. 4. If the number N gets very large (say, N=255 for B=8), the array of comparators will reserve a considerable fraction of the available limited circuit area in an integrated circuit that houses the .DELTA..SIGMA.-modulator. Although it is true that the linearity requirements for the internal Flash-type ADC in a .DELTA..SIGMA.-modulator is rather relaxed in comparison to standalone analog to digital converters (any nonlinearity is divided by the gain of the preceding integrator(s)), and consequently the comparators can be made relatively small, the prohibitively large reservation of circuit area may become a limiting factor in modern electronic devices where miniaturization is a key design factor. Additionally a very large number of parallel comparators may have a very adverse effect on the power consumption of the .DELTA..SIGMA.-modulator, since the integrator that preceeds the Flash-type ADC must be able to drive the relatively high input capacitance of such a large comparator array at a very high clock rate, which is an energy-consuming task.